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As you easily can see the performance of
the mainboard is highly depending on the memory timing you adjust
in your BIOS setup. The settings you are able to change and the
different values however differ a whole lot from chipset to
chipset and from BIOS to BIOS. Some BIOSes hardly leave it up to
you to tune up your system, others give you almost too many
settings to choose from and some BIOSes adjust the memory timing
very well after you only had to choose the DRAM speed. In general
you can say that for optimal performance you should keep most of
the values as low as possible. Should you choose them too low
however you will either occur system crashes/hangs or your system
wont boot at all. Even if this should happen there's nothing
you'll have to fear though. Just load setup defaults after
entering setup again and you can be sure your system will work
just fine - just not too fast however. Also there's no long term
damage to fear - readjust your settings and everything will be as
it was before.
The Settings
You'll find the memory timing settings
usually in the Advanced
Chipset Setup section of the BIOS
setup.
- Auto Configuration
- If you ever should want to get
the most out of your system then switch this one
off - quickly ! You anyway wont be able to change
anything unless you do.
- DRAM Read Timing
- Short Explanation:
Most accesses of the main memory are actually
happening as a Burst. This is due to the cache
not fetching only one DWord/Word/Byte, but rather
than that fetching 4 or 8 consecutive DWords in a
line. That's obviously much more effective than
getting each byte on its own into the cache or
the CPU. A burst read is done (in easy words) by
telling the memory the first address first and
then consecutive DWords can be read in a row,
without telling the memory each address anymore.
This obviously saves time. In clock cycles this
looks then like x-y-y-y for a normal burst
or x-y-y-y-z-y-y-y for a so called
back-to-back burst. For Pipelined Burst Cache RAM
e.g. this is 3-1-1-1 or 3-1-1-1-1-1-1-1. That's
the amount of clock cycles the CPU needs for
reading from its PB cache. Now for the main
memory it's not a fixed value like for the PB
cache, instead you can and have to adjust the x,y
and sometimes also the z, due to the different
DRAM types and speeds.
Now after you've read this and hopefully
understood it as well ;-), you see that the
system will be faster when the x,y,z values are
low rather than high, 'cause it takes the CPU
less clock cycles to actually get the data it
wants to process.
The DRAM Read Timing is more or less the 'y'.
Therefore you normally can choose from something
like x222 and x333 for EDO (which is faster) and x333 and x444
for FPM RAM.
You often have to choose it combined which each
other, like x222/x333 and x333/x444, where the
higher value stands for FPM, the lower for EDO
RAM.
- Recommendation:
Choose the lowest possible value and try out
your system ! If you don't occur crashes after
starting some programs (best under Windows 95 or
more sophisticated OSes) it obviously is the
right setting for your RAM.
- DRAM Write Timing
- Short Explanation:
Well, it's the same as the read timing, with
the difference that the values are the same for
FPM and EDO RAM, if you shouldn't have known, EDO
is only faster being read as FPM, the write
accesses are the same.
So also, you adjust the 'y', this time for
the read timing.
- Recommendation:
As above, as low as possible. Change it and
check your system !
- RAS to CAS Delay
- Short Explanation:
This is the amount of clock cycles it shall
take for the Ccolumn Access
Strobe to follow the Row
Access Strobe.
- Recommendation:
Again as low as possible, but again remember
that not every RAM module is able to work with
the lowest setting, so test your system after
changing it !
- DRAM Leadoff Timing
- Short Explanation:
This one is the 'x' of the above
described burst read/write. Here are some
interesting differences between the Intel Triton
FX and HX chipset. The FX can read fastest in a
burst with 7-y-y-y, the HX is able to do 5-y-y-y
- that's the reason why it's faster !
Writing in the FX is actually always done in a
5-y-y-y, the HX is also able to do a 4-y-y-y, but
Intel recommends this only for 50 or 60 MHz bus
clock.
- Recommendation:
And again keep it as low as possible. The
value '5' for the HX chipset is mainly meant to
only work well with 50ns or faster EDO.
- Turbo Read Leadoff
- Short Explanation:
Well, that seems to be a quite stupid name
for choosing the lowest Leadoff setting, most
likely '5' for HX boards. Still don't know what
turbo chargers have to do with computers...
- Recommendation:
Enabled of course, but as above be aware of
....
- Turbo Read Pipelining
- Recommendation:
Well, it sounds turbo-good to me,
enable it and see how it goes !
- Speculative Lead Off
- Short Explanation:
The 430HX chipset is capable of allowing a
DRAM read request to be generated slightly before
the address has been fully decoded. This can
reduce read latencies.
More simply, the CPU will issue a read request
and included in this request is the place
(address) in memory where the desired data is to
be found. This request is received by the DRAM
controller. When enabled, the controller will
issue the read command slightly before it has
finished determining the address.
Thanks to Novations Technologies Inc., who gave
me this info.
- Recommendation:
BY ALL MEANS enable it TO GAIN PERFORMANCE
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